Field of the Invention
The present invention relates to a frequency multiplier which multiplies electric power, for example, in a microwave or milliwave radiofrequency band.
Background Art
Japanese Patent Laid-Open No. 3-158008 discloses a frequency multiplier in which a source-grounded transistor and a gate-grounded transistor are connected in parallel with each other. From electric power of a fundamental frequency input to this frequency multiplier, the source-grounded transistor outputs electric power in the opposite phase and the gate-grounded transistor outputs electric power in phase with the input. Therefore these electric powers cancel out when combined at the output side. Electric powers of the second-order harmonic frequency which are output in phase with each other from the two transistors are taken out from an output terminal.
Japanese Patent Laid-Open No. 2001-244746 discloses the provision of damping resistors on the output sides of the two transistors for stabilization.
The frequency multiplier disclosed in Japanese Patent Laid-Open No. 3-158008 has a problem that oscillation occurs due to a negative resistance characteristic of the gate-grounded transistor exhibited in a high-frequency band such as a microwave or milliwave band.
The frequency multiplier disclosed in Japanese Patent Laid-Open No. 2001-244746 has a problem that electric power of the second-order harmonic frequency generated by the transistors is consumed by the damping resistors and a conversion gain which is a characteristic of the frequency multiplier is reduced.